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E2O0014-27-X2
Semiconductor MSM81C55-5RS/GS/JS
Semiconductor 2048-Bit CMOS STATIC RAM WITH I/O PORTS AND TIMER
This version: Jan. 1998 MSM81C55-5RS/GS/JS Previous version: Aug. 1996
GENERAL DESCRIPTION
The MSM81C55-5 has a 2k-bit static RAM (256 bytes) with parallel I/O ports and a timer. It uses silicon gate CMOS technology and consumes a standby current of 100 micro ampere, maximum, while the chip is not selected. Featureing a maximum access time of 400 ns, the MSM81C55-5 can be used in an MSM80C85AH system without using wait states. The parallel I/O consists of two 8-bit ports and one 6-bit port (both general purpose). The MSM81C55-5 also contains a 14-bit programmable counter/timer which may be used for sequence-wave generation or terminal count-pulsing.
FEATURES
* High speed and low power achieved with silicon gate CMOS technology * 256 words x 8bits RAM * Single power supply, 3 to 6 V * Completely static operation * On-chip address latch * 8-bit programmable I/O ports (port A and B) * TTL Compatible * RAM data hold characteristic at 2 V * 6-bit programmable I/O port (port C) * 14-bit programmable binary counter/timer * Multiplexed address/data bus * Direct interface with MSM80C85AH * 40-pin Plastic DIP (DIP40-P-600-2.54): (Product name: MSM81C55-5RS) * 44-pin Plastic QFJ (QFJ44-P-S650-1.27): (Product name: MSM81C55-5JS) * 44-pin Plastic QFP (QFP44-P-910-0.80-2K): (Product name: MSM81C55-5GS-2K)
FUNCTIONAL BLOCK DIAGRAM
Port A IO/M A AD0 - 7 CE ALE RD WR RESET Timer C Port C 6 PC0 - 5 256 8 Static RAM B Port B 8 PB0 - 7 8 PA0 - 7
TIMER IN TIMER OUT
VCC (+5 V) GND (0 V)
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Semiconductor
MSM81C55-5RS/GS/JS
PIN CONFIGURATION (TOP VIEW)
40 pin Plastic DIP
PC3 1 PC4 2 TIMER IN 3 RESET 4 PC5 5 TIMER OUT 6 IO/M 7 CE 8 RD 9 WR 10 ALE 11 AD0 12 AD1 13 AD2 14 AD3 15 AD4 16 AD5 17 AD6 18 AD7 19 GND 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC PC2 PC1 PC0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
44 pin Plastic QFP
42 TIMER IN 43 RESET
44 PC5
41 PC4
40 PC3
37 PC2
36 PC1
35 PC0
TIMEROUT 1 IO/M 2 CE 3 RD 4 WR 5 ALE 6 AD0 7 AD1 8 AD2 9 AD3 10 NC 11 AD4 12 AD5 13 AD6 14 AD7 15 GND 16 17 PA0 18 PA1 19 20 PA3 21 22
38 NC
34 PB7 33 PB6 32 PB5 31 PB4 30 PB3 29 PB2 28 PB1 27 PB0 26 PA7 25 PA6 24 PA5 23 PA4
39 VCC
44 pin Plastic QFJ
4 TIMER IN 5 RESET
44 VCC
6 PC5
3 PC4
2 PC3
43 PC2
42 PC1
41 PC0
VCC
TIMER OUT 7 IO/M 8 CE 9 RD 10 WR 11 NC 12 ALE 13 AD0 14 AD1 15 AD2 16 AD3 17 AD4 18 19 20 AD6 21 AD7 22 GND 23 PA0 24 PA1 25 PA2 26 PA3 27 PA4 28
40 PB7 39 PB6 38 PB5 37 PB4 36 PB3 35 PB2 34 NC 33 PB1 32 PB0 31 PA7 30 PA6 29 PA5
PA2
NC
NC
AD5
1 NC
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Semiconductor
MSM81C55-5RS/GS/JS
ABSOLUTE MAXIMUM RATING
Parameter Power Supply Voltage Input Voltage Output Voltage Storage Temperature Power Dissipation Symbol VCC VIN VOUT TSTG PD Conditions
MSM81C55-5RS
Rating
MSM81C55-5GS MSM81C55-5JS
Unit V V V C 1.0 W
Referenced to GND -- Ta = 25C 1.0
-0.5 to +7 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -55 to +150 0.7
OPERATING CONDITION
Parameter Power Supply Voltage Operating Temperature Symbol VCC TOP Range 3 to 6 -40 to +85 Unit V C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage (81C55) Operating Temperature (81C55) "L" Level Input "H" Level Input Supply Voltage (81C55-5) Operating Temperature (81C55-5) Symbol VCC TOP VIL VIH VCC VOP Min. 4.5 -40 -0.3 2.2 4.75 -40 Typ. 5 +25 -- -- 5 +25 Max. 5.5 +85 +0.8 VCC +0.3 5.25 +70 Unit V C V V V C
DC CHARACTERISTICS
Parameter "L" Level Output Voltage "H" Level Output Voltage Input Leak Current Output Leak Current Standby Current Mean Operating Current Symbol VOL VOH ILI ILO ICCS ICC IOL = 2 mA IOH = -400 mA IOH = -40 mA 0 VIN VCC 0 VOUT VCC CE VCC -0.2 V VIH VCC -0.2 V VIL -0.2 V Memory cycle time: 1 ms VCC = 4.5 V to 5.5 V Ta = -40C to 85C Condition Min. -- 2.4 4.2 -10 -10 -- Typ. Max. Unit -- 0.45 V -- -- -- -- 0.1 -- -- 10 10 100 V V mA mA mA
--
--
5
mA
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MSM81C55-5RS/GS/JS
AC CHARACTERISTICS
VCC = 4.5 V to 5.5 V, VCC = 4.75 V to 5.25 V, Ta = -40 to +80C Ta = -40 to +70C Unit 80C85AH 3MHz I/F 80C85AH 5MHz I/F
Parameter
Symbol
Remarks
Address/latch Setup Time Latch/address Holt Time Latch/read (write) Delay Time Read/output Delay Time Address/output Delay Time Latch Width Read/data Bus Floating Time Read (write)/latch Delay Time Read (write) Width Data In/write Setup Time Write/data-in Hold Time Recovery Time Write/port Output Delay Time Port Input/read Setup Time Read/port Input Hold Time Strobe/buffer Full Delay Time Strobe Width Strobe/buffer Empty Delay Time Strobe/interrupt-on Delay Time Read/interrupt-off Delay Time Port Input/strobe Setup Time Strobe/port-input Hold Time Strobe/buffer-empty Delay Time Write/buffer-full Delay Time Write/interrupt-off Delay Time Time Output Delay Time Low Time Output Delay Time High Read/data Buse Enable Delay Time Timer Cycle Time Timer Input Rise and Fall Times Timer Input Low Level Time Timer Input High Level Time WRITE to TIMER-IN for writes which start counting TIMER-IN to WRITE for writes which start counting
tAL tLA tLC tRD tAD tLL tRDF tCL tCC tDW tWD tRV tWP tPR tRP tSBF tSS tRBE tSI tRDI tPSS tPHS tSBE tWBF tWI tTL tTH tRDE tCYC tr, tf t1 t2 tWT tTW
Min. 50 30 100 -- -- 100 0 20 250 150 0 300 -- 70 50 -- 200 -- -- -- 50 120 -- -- -- -- -- 10 320 -- 80 120 200 0
Max. -- -- -- 170 400 -- 100 -- -- -- -- -- 400 -- -- 400 -- 400 400 400 -- -- 400 400 400 400 400 -- -- 80 -- -- -- --
Min. 37 30 40 -- -- 70 0 20 200 100 25 200 -- 50 10 -- 150 -- -- -- 20 100 -- -- -- -- -- 10 320 -- 40 70 200 0
Max. -- -- -- 140 330 -- 80 -- -- -- -- -- 300 -- -- 300 -- 300 300 300 -- -- 300 300 300 300 300 -- -- 80 -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Load capacitance: 150 pF
Note: Timings are measured wth VL = 0.8 V and VH = 2.2 V for both input and output.
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Semiconductor
MSM81C55-5RS/GS/JS
TIMING DIAGRAM
Read Cycle
CE IO/M tAD AD0 - 7 tAL ALE RD tLC tCC tLL Address tLA tRDE tRD tCL tRV tRDF Data Valid
Write Cycle
CE IO/M AD0 - 7 tAL ALE WR tLL tLC tWD Address tLA Data Valid tCL
tDW
tCC
tRV
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Semiconductor Strobe Input Mode
BF tSBF STROBE tSS INTR RD Input Data From Port tPHS tSI
MSM81C55-5RS/GS/JS
tRBE
tRDI tPSS
Strobe Output Mode
BF tSBE STROBE tWBF INTR WR Output Data To Port tWI tWP tSI
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Semiconductor Basic Input Mode
tRP RD Port Input Data Bus tPR
MSM81C55-5RS/GS/JS
Basic Output Mode
WR Data Bus Port Output Note: The DATA BUS timing is the same as the read and write cycles. tWP
Timer Waveforms 1
Load Counter From Count Length Register 2 TIMER IN tr TIMER OUT (Pulse) TIMER OUT (Square Wave) (Note) (Note) 1 tf t1 5 4 t2 Load Counter From Count Length Register 3 2 1 (T.C) 5
tCYC tTL tTL tTH tTH Count Down(5AE1)
Note: Periodically outut according to the output mode (m1=1) programming contents.
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Semiconductor Timer Waveforms 2
WR Timer - Start
tTW tWT
MSM81C55-5RS/GS/JS
TIMER IN
RAM DATA HOLD CHARACTERISTICS AT LOW SUPPLY VOLTAGE
Item Data Holding Supply Voltage Data Holding Supply Current Setup Time Hold Time Symbol VCCH ICCH tSU tR Condition VIN = 0 V or VCC, ALE = 0 V VCC = VCCH, ALE = 0 VIN = 0 V or VCC Specification Min. Typ. Max. 2.0 -- 30 20 -- 0.05 -- -- -- 20 -- -- Unit V mA ns ns
Two ways to place device in standby mode: (1) Method using CE
tSU 5V 4.5 V VCC Standby Mode tR
VCCH
tLA
ALE 0.8 V 0V tAL 2.2 V CE VCCH
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Semiconductor (2) Method using RESET
tSU 5V 4.5 V 2.2 V VCCH RESET VCC Standby Mode tR
MSM81C55-5RS/GS/JS
GND
Note: In this case, the C/S register is reset, the port is set into the input mode, and the timer stops.
PIN FUNCTION
Symbol RESET ALE AD0 - 7 CE IO/M RD WR PA0 - 7 (PB0 - 7) Function A high level input to this pin resets the chip, places all three I/O ports in the input mode, resets all output latches and stops timer. Negative going edge of the ALE (Address Latch Enable) input latches AD0 - 7, IO/M, and CE signals into the respective latches. Three-state, bi-directional address/data bus. Eight-bit address information on this bus is read into the internal address latch at the negative going edge of the ALE. Eight bits of data can be read from or written to the chip using this bus depending on the state of the WRITE or READ input. When the CE input is high, both read and write operations to the chip are disabled. A high level input to this pin selects the internal I/O functions, and a low level selects the memory. If this pin is low, data from either the memory or ports is read onto the AD0 - 7 lines depending on the state of the IO/M line. If this pin is low, data on lines AD0 - 7 is written into either the memory or into the selected port depending on the state of the line IO/M line. General-purpose I/O pins. Input/output directions can be determined by programming the command/ status (C/S) register. Three pins are usable either as general-purpose I/O pins or control pins for the PA and PB ports. When used as control pins, they are assigned to the following functions: PC0: A INTR (port A interrupt) PC1: A BF (port A full) PC2: A STB (port A strobe) PC3: B INTR (port B interrupt) PC4: B BF (port B buffer full) PC5: B STB (port B strobe) Input to the counter/timer Timer output. When the present count is reached during timer operation, this pin provides a square-wave or pulse output depending on the programmed control status. 3-6V power supply GND
PC0 - 5
TIMER IN TIMER OUT VCC GND
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MSM81C55-5RS/GS/JS
OPERATION
Description The MSM81C55-5 has three functions as described below. * 2K-bit static RAM (256 words 8 bits) * Two 8-bit I/O ports (PA and PB) and a 6-bit I/O port (PC) * 14-bit timer counter The internal register is shown in the figure below, and the I/O addresses are described in the table below.
8 Bit Internal Data Bus
Command Status
PC
PB
PA
Timer MSB
Timer LSB
6 Bit
8 Bit
8 Bit
Timer Mode
A7
A6
A5
I/O Address A4 A3 A2 0 0 0 0 1 1
A1 0 0 1 1 0 0
A0 0 1 0 1 0 1
Selecting Register Internal command/status register Universal I/O port A (PA) Universal I/O port B (PB) I/O port C (PC) Timer count lower position 8 bits (LSB) Timer count upper position 6 bits and timer mode 2 bits (MSB)
: Don't care.
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Semiconductor (1) Programming the Command/Status (C/S) Register
MSM81C55-5RS/GS/JS
The contents of the command register can be written during an I/O cycle by addressing it with an I/O address of xxxxx000. Bit assignments for the register are shown below:
7 TM2 6 TM1 5 IEB 4 IEA 3 PC2 2 PC1 1 PB 0 PA Definition of PA0 - 7 Definition of PB0 - 7 Definition of PC0 - 5 0= Input 1= Output 00=ALT1 11=ALT2 01=ALT3 10=ALT4 See the port control assignment table.
Port A Interrupt Enable Port B Interrupt Enable
1 = Enabled 0 = Disabled
Timer Command
00 = NOP : Does not affect counter operations. 01 = STOP : Stops the timer if it is runnning. NOP if the timer is not runnning. 10 = STOP AFTER TC : Stops the timer when it reaches TC. NOP if the timer is not running. 11 = START : If the timer is not running, loads the mode and the count length, and immediately starts timer operation. If the timer is running, loads a new mode and the count length, and starts timer operation immediately after TC is reached.
Port Control Assignment Table Pin PC0 PC1 PC2 PC3 PC4 PC5 ALT1 Input port Input port Input port Input port Input port Input port ALT2 Output port Output port Output port Output port Output port Output port ALT3 A INTR A BF A STB Output port Output port Output port ALT4 A INTR A BF A STB B INTR B BF B STB
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Semiconductor (2) Reading the C/S Register
MSM81C55-5RS/GS/JS
The I/O and timer status can be accessed by reading the contents of the Status register located at I/O address xxxxx000. The status word format is shown below:
AD7 AD6 TIMER AD5 INTE B AD4 B BF AD3 INTR B AD2 INTE A AD1 A BF AD0 INTR A
Port A Interrupt Request Port A Buffer Full Port A Interrupt Enable Port B Interrupt Request Port B Buffer Full Port B Interrupt Enable Timer Interrupt. This bit is set high when the timer reaches TC, and is reset when the C/S register is read or a hardware reset occurs.
(3) PA and PB Registers These registers may be used as either input or output ports depending on the programmed contents of the C/S register. They may also be used either in the basic mode or in the strobe mode. I/O address of the PA register: xxxxx001 I/O address of the PB register: xxxxx010 (4) PC Register The PC register may be used as an input port, output port or control register depending on the programmed contents of the C/S register. The I/O address of the PC register is xxxxx011. (5) Timer The timer is a 14-bit down counter which counts TIMER IN pulses. The low order byte of the timer register has an I/O address of xxxxx100, and the high order byte of the register has an I/O address of xxxxx101. The count length register (CLR) may be preset with two bytes of data. Bits 0 through 13 are assigned to the count length and bits 14 and 15 specify the timer output mode. A read operation of the CLR reads the contents of the counter and the pertinent output mode. The initial value range which can initially be loaded into the counter is 2 through 3FFF hex. Bit assignments to the timer counter and possible output modes are shown in the following.
M2 M1 T13 T12 T11 T10 T9 T8
Output Mode
High Order 6 Bits of Count Length
T7
T6
T5
T4
T3
T2
T1
T0
Low Order Byte of Count Length
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Semiconductor M2 0 0 M1 0 1
MSM81C55-5RS/GS/JS
1 1
0 1
Outputs a low-level signal in the latter half (Note 1) of a count period. Outputs a low-level signal in the latter half of a count period, automatically loads the programmed count length, and restarts counting when the TC value is reached. Outputs a pulse when the TC value is reached. Outputs a pulse each time the preset TC value is reached, automatically loads the programmed count length, and restarts from the beginning.
Notes: 1. When counting an asymmetrical value such as (9), a high level is output during the first period of five,and a low level is output during the second period of four. 2. If an internal counter of the MSM81C55-5 receives a reset signal, count operation stops but the counter is not set to a specific initial value or output mode. When restarting count operation after reset, the START command must be executed again through the C/S register. Note that while the counter is counting, you may load a new count and mode into the CLR. Before the new count and mode will be used by the counter, you must issue a START command to the counter. Please note the timer circuit on the MSM81C55-5 is designed to be a square-wave timer, not a event counter. To achieve this, it counts down by twos twice in completing one cycle. Thus, its registers do not contain values directly representing the number of TIMER IN pulse received. After the timer has started counting down, the values residing in the count registers can be used to calculate the actual number of TIMER IN pulse required to complete the timer cycle if desired. To obtain the remaining count, perform the following operations in order. 1. 2. 3. 4. 5. STOP the counter Read in the 16-bit value from the count registers. Reset the upper two mode bits Reset the carry and rotate right one position all 16 bits through carry If carry is set, add 1/2 of the full original count (1/2 full count-1 if full count is odd).
Note: If you started with an odd count and you read the count registers before the third count pulse occurs, you will not be able to recognize whether one or two counts have occurred. Regardless of this, the MSM81C555 always counts out the right number of pulses in generating the TIMER OUT waveforms. TIMER-IN
WR n=5 Start 5 5 3 4 2 (TC) 5 5
TIMER-OUT (Square Wave) TIMER-OUT (Pulse) WR n=4 Start
5
3
4
2 (TC)
5
3
4
TIMER-OUT (Square Wave) TIMER-OUT (Pulse) Note: n is the value set in the CLR. Figures in the diagram refer to counter values
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MSM81C55-5RS/GS/JS
(6) Standby Mode (see page 7) The MSM81C55-5 is placed in standby mode when the high level at the CE input is latched during the negative going edge of ALE. All input ports and the timer input should be pulled up or down to either VCC or GND potential. When using battery back-up, all ports should be set low or in input port mode. The timer output should be set low. Otherwise, a buffer should be added to the timer output and the battery should be connected to the power supply pins of the buffer. By setting the reset input to a high level, the standby mode can be selected. In this case, the command register is reset, so the ports automatically set to the input mode and the timer stops.
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Semiconductor
MSM81C55-5RS/GS/JS
NOTICE ON REPLACING LOW-SPEED DEVICES WITH HIGH-SPEED DEVICES
The conventional low speed devices are replaced by high-speed devices as shown below. When you want to replace your low speed devices with high-speed devices, read the replacement notice given on the next pages.
High-speed device (New) M80C85AH M80C86A-10 M80C88A-10 M82C84A-2 M81C55-5 M82C37B-5 M82C51A-2 M82C53-2 M82C55A-2
Low-speed device (Old) M80C85A/M80C85A-2 M80C86A/M80C86A-2 M80C88A/M80C88A-2 M82C84A/M82C84A-5 M81C55 M82C37A/M82C37A-5 M82C51A M82C53-5 M82C55A-5
Remarks 8bit MPU 16bit MPU 8bit MPU Clock generator RAM.I/O, timer DMA controller USART Timer PPI
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Semiconductor
Differences between MSM81C55-5 and MSM81C55 1) Manufacturing Process These devices use a 3 m Si-CMOS.
MSM81C55-5RS/GS/JS
2) Design These devices use the same chip. However, different outgoing inspection standards are used for these devices separately. 3) Electrical Characteristics ''Oki's '96 Data Book for MICROCONTROLLER'' describes that the MSM81C55-5 satisfies the electrical characteristics of the MSM81C55. As shown above, the devices can be replaced without any trouble.
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Semiconductor
MSM81C55-5RS/GS/JS
PACKAGE DIMENSIONS
(Unit : mm)
DIP40-P-600-2.54
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 6.10 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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Semiconductor
MSM81C55-5RS/GS/JS
(Unit : mm)
QFJ44-P-S650-1.27
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin Cu alloy Solder plating 5 mm or more 2.00 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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Semiconductor
MSM81C55-5RS/GS/JS
(Unit : mm) QFP44-P-910-0.80-2K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.41 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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